Goals

Things that were leftover:

  • Help Zihao start implementing Lattice FPGA model
  • Finish Xilinx model
  • Make 9 month plan for ASPLOS

Other things I want to do:

  • Finish massive PLDI Glenside PR once and for all
  • Start prototyping synthesis beyond a single slice
  • Read generals guidelines

What Do I Do?

What Am I Writing?

Reflection on Goals