Goals

We have seven weeks til our internal deadline. The biggest tasks I see left to do are:

  • Write the paper.
  • Automate all of the primitive importing across all architectures.
  • Finish and scale up LUT-based multiplication.
  • Support Lattice and SOFA DSPs.
  • Generate Pareto curves.

Concrete tasks I could do this week:

  • Get notes in introduction of paper integrated into the intro itself, so that we can group write
  • Speed up Lakeroad tests by calling Verilator as few times as possible.
  • Automate the importing of all primitives we currently use.
    • Xilinx DSP done
    • Xilinx LUTs maybe done
    • Xilinx carry not done?
    • Lattice LUTs not done
    • Lattice carry not done
    • Lattice DSP not done
    • SOFA LUTs not done
    • Other SOFA primitives not done
  • To start generating Pareto curves: make it so that all templates are being used in the evaluation, so that we’re generating multiple implementations per instruction.

With that, here’s my list, in order of priority.

  • Integrate notes into introduction.
  • Group write on introduction.
  • Speed up Lakeroad tests by limiting calls to Verilator.
  • Generate all possible implementations of each instruction in the evaluation.
  • Automate the importing of the primitives that we currently have supported manually. For now, don’t worry about the things we don’t support (Lattice DSPs, SOFA carries and DSPs). So we want to get Xilinx LUTs, Xilinx carries, Lattice LUTs, Lattice carries, SOFA LUTs.

Reflection on Goals

  • Integrate notes into introduction.
    • This was about 75% done, so I’m not marking it as done. Still had a good group-write session.
  • Group write on introduction.
  • Speed up Lakeroad tests by limiting calls to Verilator.
    • Still need to merge, have some (hopefully) minor bugs to clear up.
  • Generate all possible implementations of each instruction in the evaluation.
  • Automate the importing of the primitives that we currently have supported manually. For now, don’t worry about the things we don’t support (Lattice DSPs, SOFA carries and DSPs). So we want to get Xilinx LUTs, Xilinx carries, Lattice LUTs, Lattice carries, SOFA LUTs.

The Verilator optimization took longer than expected. The last two tasks I’ll focus on next week.