Gus Henry Smith
email@example.com – justg.us
Paul G. Allen Center for Computer Science & Engineering
Pursuing Ph.D., coadvised by Luis Ceze and Zach Tatlock. Focus: using tools from Programming Languages to automatically generate compilers for custom hardware.
The Schreyer Honor’s College
M.S./B.S. in Computer Science and Engineering. Advised by Vijay Narayanan and John Sampson.
Specialized Accelerators and Compiler Flows: Replacing Accelerator APIs with a Formal Software/Hardware Interface. Arxiv 2022 (link). Bo-Yuan Huang, Steven Lyubomirsky, Yi Li, Mike He, Thierry Tambe, Gus Henry Smith, Akash Gaonkar, Vishal Canumalla, Gu-Yeon Wei, Aarti Gupta, Zachary Tatlock, Sharad Malik. (The 3LA paper.)
Pure Tensor Program Rewriting via Access Patterns (Representation Pearl). MAPS 2021. Gus Henry Smith, Andrew Liu, Steven Lyubomirsky, Scott Davidson, Joseph McMahan, Michael Taylor, Luis Ceze, Zachary Tatlock. (The Glenside paper.)
From DSLs to Accelerator-Rich Platform Implementations: Addressing the Mapping Gap. LATTE 2021. Bo-Yuan Huang, Steven Lyubomirsky, Thierry Tambe, Yi Li, Mike He, Gus Smith, Gu-Yeon Wei, Aarti Gupta, Sharad Malik, Zachary Tatlock.
Enumerating Hardware-Software Splits with Program Rewriting. YArch 2020. Gus Smith, Zachary Tatlock, Luis Ceze.
A FerroFET-Based In-Memory Processor for Solving Distributed and Iterative Optimizations via Least-Squares Method. IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 2019. Insik Yoon, Muya Chang, Kai Ni, Matthew Jerry, Samantak Gangopadhyay, Gus Henry Smith, Tomer Hamam, Justin Romberg, Vijaykrishnan Narayanan, Asif Khan, Suman Datta, Arijit Raychowdhury.
Designing Processing in Memory Architectures via Static Analysis of Real Programs. MS Thesis, 2018.
Computing With Networks of Oscillatory Dynamical Systems. Proceedings of the IEEE, 2018. Arijit Raychowdhury, Abhinav Parihar, Gus Henry Smith, Vijaykrishnan Narayanan, György Csaba, Matthew Jerry, Wolfgang Porod, Suman Datta.
A FeFET Based Processing-In-Memory Architecture for Solving Distributed Least-Square Optimizations. DRC 2018. Insik Yoon, Muya Chang, Kai Ni, Matthew Jerry, Samantak Gangopadhyay, Gus Smith, Tomer Hamam, Vijayakrishan Narayanan, Justin Romberg, Shih-Lien Lu, Suman Datta, Arijit Raychowdhury.
Third Eye: A Shopping Assistant for the Visually Impaired. IEEE Computer, 2017. Peter A Zientara, Sooyeon Lee, Gus H Smith, Rorry Brenner, Laurent Itti, Mary B Rosson, John M Carroll, Kevin M Irick, Vijaykrishnan Narayanan.
since Fall 2021
Lead Researcher; UW SAMPL Lab/UW PLSE Lab/Real-time Machine Learning
Automatically synthesizing target-specific FPGA dialect implementations for various FPGAs from a functional description of the FPGA architecture using solver-aided programming (via Rosette). Exploring potential FPGA dialects using program rewriting via equality saturation with egg.
since Winter 2020
Contributor; UW PLSE Lab, w/ colleagues at Princeton and Harvard
Designing a methodology
for verifiably mapping deep learning models to
custom accelerators. Utilizing Glenside to expose mappings in workloads.
Lead Researcher; UW SAMPL Lab/Real-time Machine Learning
Designed a pure, binder-free intermediate language for optimizing low-level tensor programs via program rewriting. (See Pure Tensor Program Rewriting via Access Patterns.) Used the language to map computations to custom hardware. (See Specialized Accelerators and Compiler Flows: Replacing Accelerator APIs with a Formal Software/Hardware Interface.)
Lead Researcher; UW SAMPL Lab
Enabled the exploration of new, nontraditional datatypes (i.e., alternatives to IEEE 754 floating point) with an extension to TVM, a deep learning compiler. My qualifying exam project for my Ph.D.
Static Analysis for Processing in Memory Accelerator Design
Master’s Project; PSU Microsystems Design Lab
Given a model of accelerating computation using processing in memory, used LLVM to detect potentially offloadable code sections within workloads.
ThirdEye: Shopping Assistant for the Visually Impaired
Contributor, Lead Researcher; PSU Microsystems Design Lab
Built a wearable system to assist the visually impaired in shopping. My undergraduate research.
Fall 2021–Summer 2022
Student Researcher (part-time)
Continued my previous work developing a learned cost model for configuring sparse tensor kernels.
Software Engineering Intern, MLIR
Developed a learned cost model for configuring sparse tensor kernels. In addition, contributed to the MLIR sparse tensor dialect.
Research Intern, AI and Advanced Architectures
Statically analyzed deep learning workloads to inform architecture design.
Software Engineering Intern, Fuchsia
Implemented the RFCOMM protocol for one of Google’s OSes, Fuchsia.
Software Engineering Intern, Chrome
Helped the Chrome Remote Desktop team identify and implement optimizations for embedded devices such as the Raspberry Pi.
Software Engineering Intern, Android Internal Tools
Contributed to Java-based Android profiling tools.
- SCF22 Reviewer
- LATTE 2022 Reviewer
- SIGPLAN-M Mentor
- POPL 2021 Artifact Evaluator
- ASPLOS 2020 Artifact Evaluator
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